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fiber optics december 2000 v23816-n1018-c312/l312 (*) 3.3 v, 4-line lvds parallel 2.5 gbd transponder oc-48 sonet/sdh short reach (sr) up to 2 km preliminary features ? compliant with existing standards compact integrated transponder unit with ? fp laser diode transmitter ? ingaas pin photodiode receiver ? pigtailed optical connections ? integrated mux, demux and clock recovery class 1 fda and iec laser safety compliant single +3.3 v power supply oc-48 optical transmit and receive at 2488.32 mbit/s 4-line lvds differential interface at 622.08 mbit/s external control for laser shutoff loss of optical signal and loss of synch indicators (rx) loss of lock indicator for tx high speed clock laser bias monitor rx power monitor output loopback operating modes 155.520 mhz lvpecl input tx reference clock 2.6 w typical power consumption tx fault output indicator absolute maximum ratings operation beyond these ratings may cause permanent damage to the transponder. supply voltage (v cc ).................................................... 0 to 4.0 v lvds input levels.......................................................... 0 to v cc lvpecl input level ...................................................... 0 to v cc lvttl input level ........................................................ 0 to 5.5 v lvds output source current............................................. 5 ma lvpecl output source current....................................... 24 ma lvttl output source current ........................................... 1 ma operating ambient temperature ................................ 0 to 70 o c storage ambient temperature ............................... ?40 to 85 c static discharge voltage, all pins ................................... 1000 v (*) ordering information dimensions in [mm] inches connector type fiber length part number sc 24.1 0.8 ? v23816-n1018-c312 lc 24.1 0.8 ? V23816-N1018-L312
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 2 description the infineon single mode sonet/sdh transponder is compli- ant with the bellcore gr-253, itu-t g.957, and itu-t g.958 specifications. it is also compliant with the oif99.102 proposal. the transmitter section consists of a multiplexer (mux), laser driver, fabry perot (fp) laser diode and pigtail single mode fiber with lc/pc or sc/pc 0 termination. the receiver section consists of a multimode fiber pigtail with lc/pc or sc/pc termi- nation, a packaged pin photodiode and preamplifier, postampli- fier, clock and data recovery (cdr), and a demultiplexer (demux). the mux and demux functions are integrated together onto a single transceiver ic. the 622.08 mhz parallel data interface frees the user from the concerns of pcb layout at 2.5 gb/s. the pluggable connector blind mates easily to the customer pcb, and allows the transponder to be removed prior to any solder reflow or washing of the users pcb. the transponder operates from a single +3.3 v power supply. the electrical interface is via a 60 pin pluggable connector. the transmit and receive electrical signals each consist of 4 parallel differential lvds data, and a differential lvds clock. the trans- mit input data and clock lines, and the receive output data and clock lines, are all internally biased and terminated. all lines are dc coupled to the interface connector. the transponder is designed to transmit and receive serial oc- 48 (2488.32 mb/s) data over standard non-dispersion-shifted single mode fiber at a wavelength of 1310 nm. transmitter (mux section) please refer to the transponder block diagram. the transmitter accepts a 4 bit wide parallel input data word, txdatap/n[3:0], at a 622.08 mb/s data rate. the tx input clock, txclkp/n, is synchronous with the incoming data, at a fre- quency of 622.08 mhz. this clock is used to load the data into a 4-bit latch. the data is read in on the rising edge of the positive input clock. (see tx input timing diagram). a reference input clock, refclkp/n, at 155.52 mhz, is sup- plied as a reference input to the high speed clock synthesizer. the high speed output of the clock synthesizer will clock the timing generator and the parallel-to-serial converter. the paral- lel-to-serial converter will output the retimed data as a serial bit stream, tsdp/n, at 2488.32 mb/s data rate. bit 3 of the txdatap/n parallel input word is the msb, and is transmitted first in the data stream. bit 0, the lsb, is transmitted last. the output of the high speed clock synthesizer, which is inter- nally set to 2488.32 mhz, is tapped off the timing generator, and is divided to 622.08 mhz. this output (pclkp/n) is intended to be used as a reference clock for tx upstream logic. the phase_initp/n input signal is used to realign the internal timing of the timing generator by resetting and centering the fifo in the transceiver ic. the realignment will occur on the ris- ing edge of phase_initp , which must be held high for at least 10 ns. the phase_errp/n output will pulse high during each clock cycle when there is a potential set-up & hold timing violation between the internal byte clock and the txclkp/n input, indi- cating that phase_initp/n must be strobed. if the reference clock input, refclkp/n, is derived from and is synchronous with the tx byte clock, txclkp/n, then there should never be any short setup and hold times between the two timing domains, and the fifo should never need to be recentered. however, if the refclkp/n input is, for instance, produced by a free running oscillator, then such potential viola- tions may exist. when fifo realignment occurs, up to 10 bytes of data will be lost. automatic fifo realignment can be enabled by simply connecting the phase_errp/n output directly to the phaseinitp/n input. the user can also take the phase_errp/ n output, process it and send a signal to the phase_initp/n in such a way that idle bytes are lost during the realignment pro- cess. the tx clock synthesizer section provides a lock alarm output signal, txlock, which indicates if the clock synthesizer is prop- erly phase locked. transmitter (electro-optical section) the serial data output, tsdp/n, of the transceiver ic is input to a laser driver ic. the laser driver provides both bias and modula- tion to a laser diode. the laser bias current is controlled by a closed-loop circuit, which regulates the output average power of the laser over conditions of temperature and aging. the mon- itor pin diode, which is mechanically built into the laser, pro- vides a feedback signal to the laser driver, and prevents the laser power from exceeding the factory preset operating limits. the laser driver includes an eye safety feature that will automat- ically shut off power to the laser if a fault condition occurs which causes excessively high laser bias current or excessively high average output power. such a fault will be indicated on the tx_fault output. the fault can be cleared by cycling dc power, or by strobing the reset_l input. the mux and laser driver can be reset with the reset_l input. during the time that reset_l is held active, there will be no optical output from the transmitter. the reset_l input will clear any fault indication that has occurred on the tx_fault output. the laser can be switched off at any time with the laser_disable input. the tx_biasmon output is provided as an alarm to indicate if the laser bias current is outside of the normal operating range. this output can be used to monitor the aging of the laser. the laser diode is a fabry-perot type, which, due to the cavity nature of its design, will emit light at several longitudinal wave- lengths, or modes centered about 1310 nm. this type of laser is suitable for the short reach transmission over single-mode fiber that this transponder is intended for. the laser has a single- mode fiber pigtail, which is terminated in an lc/pc 0 optical connector. receiver (electro-optical section) the input light to the rx is coupled from the transmission fiber into a pin/preamp assembly on the transponder. the pin/ preamp contains a multi-mode fiber pigtail, which is terminated in an lc/pc or sc/pc 0 optical connector. the multi-mode fiber pigtail has a larger core diameter (50 m) than the single- mode transmission fiber (9 m). therefore, all the light from the single-mode fiber is coupled into the larger diameter core of the multi-mode pigtail. the pin/preamp contains a pin photodiode, trans-impedance amplifier and non-limiting post-amplifier in one package. the pin diode produces a current output, which is directly propor-
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 3 tional to the intensity of the incoming light. the trans-imped- ance amplifier performs current-to-voltage conversion, and the non-limiting post-amplifier quantizes the signal into a digital out- put. the receiver contains a rx power monitor output, which is a voltage output directly proportional to the average optical input power. the limiting post-amplifier provides additional voltage amplifi- cation, and also provides a loss of signal (rx_los) indicator. los will occur at a rx input power level less than the specified rx sensitivity, and is an indication that the rx is taking bit errors. the clock and data recovery (cdr) uses a pll based approach to recover the high speed clock from the incoming serial data stream. a lock alarm, rx_losync, indicates if the cdr has lost synchronization. this will occur if the input rx power level is very low (below the los threshold level), or if the input data rate is outside the specified frequency tolerance. in these cases, the cdr will phase lock to a crystal oscillator so it can produce a valid clock output, with a frequency accuracy of 20 ppm. in both cases of loss of signal or loss of synchroniza- tion, the transceiver ic will force all the rx output data bits, rxdatap/n [3:0] to a constant zero state. receiver (demux section) the incoming serial data is latched into the transceiver ic by the recovered clock. the data and clock are applied to a 4 bit wide serial-to-parallel converter (demux), which demultiplexes the data into a parallel format. the first bit received, i.e. the msb which is transmitted first in the serial data stream, is placed into the highest order bit of the parallel output word, i.e. bit 3 = msb. the transceiver ic, however, does not perform a frame alignment function. this means that the parallel output word will contain the bits in the correct order, however, the position of the bits within the parallel output word may be shifted by an arbitrary amount between 0 and 4 bits. it is the function of downstream framer logic to realign the bits. the retimed rx output data, rxdatap/n[3:0], is output at a 622.08 mb/s data rate. the output clock, rxclkp/n, is at 622.08 mhz. the rxdatap/n[3:0] data is updated on the falling edge of rxclkp . (see rx output timing diagram). loopback operation four loopback modes of operation are provided. line loopback is enabled with the lleb_l input. in line loop- back operation, the rx serial data and clock inputs to the transceiver ic (rsdp/n and rsclkp/n) are routed directly to the tx serial outputs of the ic (tsdp/n and tsclkp/n). this effectively eliminates the transceiver ic from the signal path. diagnostic loopback is enabled with the dleb_l input. in diag- nostic loopback operation, the tx output serial data and clock of the transceiver ic (tsdp/n and tsclkp/n) are routed directly to the rx serial data and clock inputs of the ic (rsdp/ n and rsclkp/n). this effectively eliminates the optical and electro-optical components from the signal path. reference loop time is enabled with the rlptime input. in reference loop time operation, a divide-by-4 version of the poclkp/n output of the rx is used as the reference clock input to the tx. serial loop time is enabled with the slptime input. in serial loop time operation, the recovered high-speed clock (rsclkp/ n) from the rx section is used in place of the synthesized transmit clock. jitter the transponder is specified to meet the sonet jitter perfor- mance as outlined in itu-t g.958 and bellcore gr-253. jitter generation is defined as the amount of jitter that is gener- ated by the transponder. the jitter generation specifications are referenced to the optical oc-48 signals. if no or minimum jitter is applied to the electrical inputs of the transmitter, then jitter generation can simply be defined as the amount of jitter on the tx optical output. the sonet specifications for jitter generation are 0.01 ui rms, maximum and 0.1 ui p-p, maxi- mum. both are measured with a 12 khz-20 mhz filter in line. a ui is a unit interval, which is equivalent to one bit slot. at oc- 48, the bit slot is 400 ps, so the jitter generation specification translates to 4 ps rms, max. and 40 ps p-p, max. jitter tolerance is defined as the amount of jitter applied to the rx optical input that the receiver will tolerate while producing less than a 1 db penalty in rx sensitivity. the minimum jitter tolerance levels are normally expressed as a mask of jitter amplitude versus jitter frequency. measured jitter tolerance levels must be greater than the mask limits. the jitter toler- ance mask specified in the bellcore gr-253 document covers jitter frequencies down to 10 hz. the transponder will be designed to meet this mask. sonet jitter transfer mask (itu-t g.958 & bellcore gr-253) sonet jitter tolerance mask (bellcore gr-253) jitter transfer is defined as the ratio of output jitter to input jit- ter. referenced to an optical transponder, it is defined as the ratio of tx optical output jitter to rx optical input jitter. to measure jitter transfer, the transponder must be operating in electrical loopback mode, with the rx electrical outputs looped back into the tx electrical inputs. jitter transfer is defined to be less than 0.1 db up to 2 mhz, then dropping at ?20 db decade thereafter, per itu-t g.958 and bellcore gr-253. the jitter transfer must be less than the following mask limits.
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 4 block diagram functional signal description transmit functions tran sceiver ic refclkp/n 155.52 mhz diff lv pecl refclkp/n clock synthes izer clocks lvttl lockdet txlock high=locked timing generator high= phase error 4:1 parallel to serial converter pinp/n[3:0] 622.08 m b/sec diff lvds txdatap/n [3:0] bit3= msb piclkp/n diff lvds 622.08 mhz txclkp/n txdp/n latch tsdp/n rsclkp/n tsclkp/n low= line l oopback enabled lvttl timing generator poclkp/n rxclkp/n diff lvds 622.08 mhz 1:4 serial to parallel converter poutp/n [3:0] rxdatap/n [3:0] diff lvds 622.08 mhz latch r dleb lvttl low= diagn ostic loopback e nabled rsdp/n rsclkp/n latch sdlvpecl logic "1" sdlvttl logic lvttl txclkp/n (in ternal) cml cml laser_di sable lvttl high= disable laser laser driver lvttl tx_fault high= tx fault (a uto shutoff) fp laser diode monitor diode lvttl tx_bia smon high= tx bias current outside l imits oc-48 2488.32 m b/sec 1310 nm lc/pc clock & data recovery data clock crystal oscillator limiting post amp data data los lvttl rx_los high= rx loss of signal lock lvttl rx_losync high= rx loss of synch pin diode & preamp data oc-48 2488.32 mb/sec 1310 nm lc/pc single mode fiber lleb bit3= msb cml lvpecl 1 0 1 0 0 1 1 0 155.52 mhz diff lvpecl post amp/cdr rlptime high=ref loop time lvttl 0 1 slptime high=serial l oop time lvttl pclkp/n diff lvds pclkp/n 622.08 mhz +/- 20 ppm high=rx fault vlos 1 0 poclk div 4 rsclkp/n phinitp/n pherrp/n phase_er rp/n diff lvds diff lvds phase_in itp/n data lleb_l dleb_l reset_l lvttl reset_l +3.3v 1 2 3 signal name level i/o pin # description txdatap0 txdatan0 txdatap1 txdatan1 txdatap2 txdatan2 txdatap3 txdatan3 lvds i 1 3 7 9 13 15 19 21 transmit parallel input data at 622.08 mb/s, aligned to the txclkp/n parallel input clock. txdatap/n[3] is the most significant bit (msb), and is the first bit transmit- ted in the outgoing oc-48 serial data stream. tx- datap/n[3:0] is sampled on the rising edge of tx- clkp. dc coupled and in- ternally terminated. txclkp txclkn lvds i 27 25 transmit parallel input clock, 622.08 mhz, to which txdatap/n[3:0] is aligned. txclk transfers the data on the txdatap/ n inputs into a 4-bit wide latch in the transceiver ic. data is sampled on the ris- ing edge of txclkp. dc coupled and internally ter- minated. refclkp refclkn lvpecl i 31 33 155.52 mhz transmit ref- erence clock input to the bit clock frequency synthe- sizer of the transceiver ic. dc coupled and internally biased. phase_initp phase_initn lvds i 37 39 phase initialization. rising edge of phase_initp will realign internal timing. dc coupled. no internal termi- nation. laser_ disable lvttl i 49 laser disable. control in- put to disable transmit la- ser. high = disable laser. pulled low through 1 k ? = resistor. txlock lvttl o 51 loss of lock alarm for tx pll of the transceiver ic. high = locked. asynchro- nous output. phase_errp phase_errn lvds o 45 43 phase error. active high. phase_errp will pulses high during each clock cy- cle for which there is a po- tential set-up and hold timing violation between the internal byte clock of the transceiver ic and the txclk timing domains. dc coupled and internally terminated. signal name level i/o pin # description
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 5 receive functions loopback modes dc power tx_fault lvttl o 53 transmit fault alarm out- put. indicates that the laser has been automatically shut off due to a fault in the tx laser circuit. high = tx fault. fault may be cleared by cycling dc power, or by strobing the reset_l in- put. tx_biasmon lvttl o 59 transmit bias monitor alarm output. indicates that the bias current of the tx laser is currently outside normal operating limits. high = tx bias outside lim- its. pclkp pclkn lvds o 10 8 622.08 mhz parallel clock output. generated by divid- ing the internal high-speed tx clock by 4. reset_l lvttl i 56 master reset input. a low level resets the tx mux and laser driver. reset_l must be held low for at least 6 millisec. pulled high through a 1 k ? resistor. signal name level i/o pin # description rxdatap0 rxdatan0 rxdatap1 rxdatan1 rxdatap2 rxdatan2 rxdatap3 rxdatan3 lvds o 44 42 34 32 28 26 22 20 parallel output data at 622.08 mb/s from the re- ceiver, aligned to the parallel output clock (rxclkp/n). rxdatap/n[3] is the most significant bit, and is the first bit received in the incoming oc-48 serial data stream. rxdatap/n[3:0] is updated on the falling edge of rx- clkp. all data outputs are forced to zero level under loss of signal or loss of synchronization conditions. dc coupled outputs. internal- ly terminated. rxclkp rxclkn lvds o 16 14 parallel output clock from the receiver at 622.08 mhz. this clock is aligned to the rxdatap/n[3:0] parallel out- put data. rxdatap/n[3:0] is updated on the falling edge of rxclkp. clock output is continuous under loss of signal or loss of synchroni- zation conditions. dc cou- pled output. internally terminated. rx_los lvttl o 55 receive loss of signal alarm output. a high output level indicates rx input power is below the sensitivity level of the receiver (high ber condi- tion). signal name level i/o pin # description rx_losync lvttl o 57 receive loss of synchroni- zation alarm output. a high output level indicates that the receive clock recovery unit has lost synchronization, due to either very low rx in- put power level, or input data rate outside of frequency tol- erance. rx_mon analog o 58 receive power monitor output. a voltage output which is directly proportional to the optical rx input power. signal name level i/o pin # description lleb_l lvttl i 38 line loopback enable input. a low level enables line loopback mode. when active, the rx inputs to the transceiver ic will be routed directly to the tx outputs. pulled high through a 1 k ? resistor. dleb_l lvttl i 40 diagnostic loopback enable input. a low level enables diagnostic loopback mode. when active, the tx outputs of the transceiver ic are routed directly to the rx in- puts. pulled high through a 1 k ? re- sistor. rlp- time lvttl i 4 reference loop time enable in- put. a high level enables refer- ence loop time. when active, a divide-by-4 version of the po- clkp/n output of the rx is used as the reference clock input to the tx. pulled low through a 1 k ? resistor. slp- time lvttl i 2 serial loop time enable input. a high level enables serial loop time. when active, the recovered high-speed clock (rsclkp/n) from the rx section is used in place of the synthesized transmit clock. pulled low through a 1 k ? resistor. signal name level i/o pin # description ground 0 v dc i 5,6, 11,12, 17,18, 23,24, 29,30, 35,36, blade ground connection for both signal and chassis ground on the transponder. the blade contact of the 60 pin interface connector is tied to ground in the transponder. therefore, the blade of the user?s mating connector should be connected to ground, as well. v cc +3.3 v dc i 41,47, 46,48, 50,52, 54 dc power input. +3.3 v dc, nominal. signal name level i/o pin # description
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 6 functional diagrams tx input timing diagram rx output timing diagram te c h n i c a l d a t a recommended operating conditions note 1. t case is measured on top of the transponder (see details on page 1, outline dimensions) for t ambient below 50 c no airflow is required. for t ambient 50 c - 70 c a minimum airflow of 300 lfm (1.5 m/s) is required. please note: installation of multiple transponders require the total airflow. dc electrical characteristics parameter symbol min. typ. max. units operating case tempera- ture (1) t c 070 o c transponder total power consumption p tot 2.6 2.9 w 3.3 v supply voltage v cc 3.13 3.3 3.46 v 3.3 v supply current i cc 0.79 0.89 a input differential noise, all pins n diff 15 mv 0-p parameter symbol min. typ. max. units lvds input high volt- age lvds v ih 1.1 1.9 v lvds input low volt- age lvds v il 0.6 1.5 lvds input voltage differential lvds v indiff 200 1200 mv lvds input single ended voltage lvds v insing 100 600 lvds differential in- put resistance lvds r diff 80 100 120 ? lvds output high voltage lvds v oh 1.13 1.8 v lvds output low voltage lvds v ol 0.7 1.4 lvds output differ- ential voltage lvds v outdiff 440 740 1100 mv lvds output single ended voltage lvds v outsin- gle 220 370 550 lvpecl input low voltage lvpecl v il v cc ?1.9 v cc ?1.4 v lvpecl input high voltage lvpecl v ih v cc ?1.1 v cc ?0.55 lvpecl input single ended swing lvpecl v insingle 200 1200 mv lvpecl input differ- ential swing lvpecl v indiff 400 2400 lvpecl input dc bias lvpecl v bias v cc ?0.5 v cc ?0.3 v lvttl input high voltage lvttl v ih 2.0 v cc lvttl input low voltage lvttl v il 00.8 lvttl input high current lvttl i ih 50 a lvttl output current lvttl i o ?500 lvttl output high voltage lvttl v oh 2.4 v lvttl output low voltage lvttl v ol 0.8
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 7 ac electrical characteristics notes 1. t case is measured on top of the transponder (see details on page 1, outline dimensions) for t ambient below 50 c no airflow is required. for t ambient 50 c - 70 c a minimum airflow of 300 lfm (1.5 m/s) is required. please note: installation of multiple transponders require the total airflow. 2. maximum allowable jitter on the reference clock input (refclkp/n) such that the transmitter will meet itu-t g.958 and bellcore gr-253 jitter generation requirements. measured with a 12 khz - 20 mhz filter. parameter sym- bol condi- tions min. typ. max. units transmitter txdatap/n[3:0] input bit rate 622.08 mb/s txclkp/n input frequency 622.08 mhz txclkp/n input duty cycle 40 60 % txclkp/n input rise/fall time 20-80% 100 300 ps txdata setup time with re- spect to the ris- ing edge of txclkp t st see tx timing dia- gram 200 txdata hold time with re- spect to the ris- ing edge of txclkp t ht see tx timing dia- gram 200 refclkp/n in- put frequency 155.520 mhz refclkp/n in- put frequency tolerance 20 ppm refclkp/n in- put duty cycle 45 55 % refclkp/n in- put rise/fall time 10-90% 500 ps refclkp/n in- put jitter (2) 1ps, rms phase_initp/n input min. pulse width 3.2 ns pclkp/n out- put frequency 622.08 mhz pclkp/n out- put duty cycle 45 55 % return loss, all ac inputs & out- puts 10 mhz - 1 ghz 15 db reset_l input min. pulse width 6ms parameter sym- bol condi- tions min. typ. max. units receiver rxdatap/n[3:0] output bit rate 622.08 mb/s rxclkp/n out- put frequency 622.08 mhz rxclkp/n out- put duty cycle 40 60 % rxclkp/n out- put rise/fall time 20-80% 100 300 ps rxdata setup time with re- spect to the ris- ing edge of rxclkp t sr see rx timing dia- gram 600 rxdata hold time with re- spect to the ris- ing edge of rxclkp t hr see rx timing dia- gram 600 return loss, all ac inputs & out- puts 10 mhz - 1 ghz 15 db rxclkp/n out- put frequency accuracy during los or lo- sync (1) over operat- ing temp range 20 ppm
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 8 transmitter electro-optical characteristics notes 1. the laser driver contains a control circuit, which regulates the aver- age optical output power. nominal output power is factory set to be within the specified range. 2. the eye diagram is compliant with bellcore gr-253 and itu-t g.957 eye mask specifications. 3. jitter generation is defined as the amount of jitter on the tx optical output, when there is no or minimum jitter on the tx electrical inputs. jitter generation is compliant with gr-253 and itu-t g.958 specifications, when measured using a 12 khz - 20 mhz filter, and with a jitter level on the refclkp/n input which is less than the level specified in ? ac electrical characteristics - transmitter ? . 4. if the +3.3 v power supply drops below the specified level, the laser bias and modulation currents will be held disabled until the supply voltage rises above threshold and after the power on delay time period. 5. a fault, such as high laser bias current or high average power, which lasts longer than the specified fault delay time, will cause the trans- mitter to be disabled. the fault can be cleared by cycling of dc power, or by strobing the reset_l input. receiver electro-optical characteristics notes 1. average rx power for a 1x10 ? 10 ber, and using a prbs pattern of 2 23 ? 1 length with 72 zeros and 72 ones inserted, as per itu-t g.958. 2. jitter tolerance is defined as the amount of jitter applied to the rx optical input that the receiver will tolerate without producing bit errors. the minimum required jitter tolerance for a 1 db power pen- alty is defined to be 15 ui from 10 hz to 600 hz, 1.5 ui from 6 khz to 100 khz, and 0.15 ui from 1 mhz onwards, per bellcore gr-253. 3. jitter transfer is defined as the ratio of tx output jitter to rx input jitter, when the transponder is operated in electrical loopback mode (rx electrical outputs looped back into tx electrical inputs). jitter transfer is specified to be less than 0.1 db up to 2 mhz, and drop- ping at ? 20 db/decade after that point, per itu-t g.958 and bellcore gr-253. 4. the rx_los output is an active high lvttl output, which is set high if there is a loss of rx optical signal input (los), a decrease in optical input power below the assert level will cause the rx_los parameter symbol min. typ. max. units nominal center wave- length tx nom 1310 nm range of center wave- lengths tx min - max 1260 1360 spectral bandwidth tx ? rms 5nm, rms average output power (1) tx p avg ? 11 ? 4 ? 3dbm extinction ratio tx er 8.2 14 db output rise time 20%-80% tx t r 100 200 ps output fall time 80%-20% tx t f 175 250 eye diagram (2) tx ed tx jitter generation, rms (3) tx j gen rms 0.007 0.01 ui rms tx jitter generation, p-p (3) tx j gen p-p 0.075 0.1 ui p-p reset threshold for v cc (4) tx v th 2.2 2.95 v power on delay for v cc (4) tx t pod 20 ms fault delay (5) tx t fault 20 tx bias monitor switch- ing threshold tx i bias 60 ma parameter symbol min. typ. max. units nominal center wavelength rx nom 1310 nm sensitivity (average power) (1) rx p sens ? 25 ? 18 dbm overload (average power) (1) rx p ol ? 3 optical return loss rx rl 27 db rx jitter tolerance (2) rx j tol rx-to-tx jitter trans- fer (3) rx-tx j xfr optical path penalty rx p pen 1.0 db clock recovery cap- ture frequency range (5) rx f capt 200 ppm clock recovery ac- quisition lock time rx t lock 32 250 s rx_los output as- sert relative to rx optical input power (4) rx_ los assert ? 30 ? 25 dbm rx_losync output assert relative to rx input frequency (5) rx_ losync as- sert 450 600 770 ppm rx_los output hys- teresis (4) rx_ los hyst 3db rx_los & rx_losync output assert time (4, 5) rx t assert 100 s rx_los & rx_losync output deassert time (4, 5) rx t deassert 100 rx_mon transfer slope (6) 4.4 mv/ w rx_mon dark offset voltage (6) 53 mv rx_mon output voltage at p in = ? 17 dbm (6) 142 rx_mon output voltage at p in = ? 7 dbm (6) 900
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 9 output to switch high (on). hysteresis occurs when the optical input power is raised back above the threshold switching level. the rx_losync output is an active high lvttl output, which is set high if the clock data recovery pll becomes unlocked. loss of sync will occur at a lower optical input power level than los, but still within the specified input power range. 5. the receiver lock range is typically 300 ppm from nominal oc-48 data rate. when the data rate of the rx signal deviates by more than 600 ppm (typically) from nominal, or if the rx is in a loss of signal (los) condition, then the clock recovery module will lock to an internal 155.52 mhz crystal oscillator. under this condition: the appropriate fault output (rx_los or rx_losync) switches active; the rxdatap/n[3:0] output data is forced to all zeros; and, the switching of the rxclkp/n output is done so that the clock is con- tinuous, and there are no violations of the minimum pulse width and period. 6. rx_mon ouput voltage is measured between v cc (+) and rx_mon ( ? ). rx_mon is specified up to a maximum optical input average power of ? 5 dbm (316.2 w). connector pin assignments agency certifications typical rx_mon characteristic (linear) typical rx_mon characteristic (logarithmic) pin # signal name pin # signal name 1 txdatap0 2 slptime 3 txdatan0 4 rlptime 5 gnd 6 gnd 7 txdatap1 8 pclkn 9 txdatan1 10 pclkp 11 gnd 12 gnd 13 txdatap2 14 rxclkn 15 txdatan2 16 rxclkp 17 gnd 18 gnd 19 txdatap3 20 rxdatan3 21 txdatan3 22 rxdatap3 23 gnd 24 gnd 25 txclkn 26 rxdatan2 27 txclkp 28 rxdatap2 29 gnd 30 gnd 31 refclkp 32 rxdatan1 33 refclkn 34 rxdatap1 35 gnd 36 gnd 37 phase_initp 38 lleb_l 39 phase_initn 40 dleb_l 41 vcc 42 rxdatan0 43 phase_errn 44 rxdatap0 45 phase_errp 46 vcc 47 vcc 48 vcc 49 laser_disable 50 vcc 51 txlock 52 vcc 53 tx_fault 54 vcc 55 rx_los 56 reset_l 57 rx_losync 58 rx_mon 59 tx_biasmon 60 spare blade gnd feature standard comments emission: electromagnetic interference (emi) fcc part 15, class b en 55022 class b cispr 22 noise frequency range: 30 mhz to 13 (18) ghz immunity: radio frequency electromagnetic field en 61000-4-3 iec 61000-4-3 with a field strength of 10 v/m rms, noise frequency ranges from 10 mhz to 1 ghz. no effect on transponder performance between the specification limits. electrostatic discharge (esd) to the electrical pins iec 61000-4-2 discharges ranging from 2 kv to 15 kv with no damage to transponder. 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 0 0,1 0,2 0,3 rx input average power (mw) rx_mon voltage (v) 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 -25 -20 -15 -10 -5 rx input average power (dbm) rx_mon voltage (v)
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 10 eye safety this laser based single mode transponder is a class 1 product. it complies with iec 60825-1 and fda 21 cfr 1040.10 and 1040.11. the transponder has been certified with fda under accession number 9911449-03. to meet laser safety requirements the transponder shall be operated within the absolute maximum ratings. caution all adjustments have been made at the factory prior to ship- ment of the devices. no maintenance or alteration to the device is required. tampering with or modifying the performance of the device will result in voided product warranty. note failure to adhere to the above restrictions could result in a modifica- tion that is considered an act of ? manufacturing, ? and will require, under law, recertification of the modified product with the u.s. food and drug administration (ref. 21 cfr 1040.10 (i)). laser data required labels laser emission application notes interfacing the 4-line transponder scope this application note is meant to define the interfacing between the infineon 4-line oc-48 transponder, and the cus- tomer equipment. introduction the signals which interface to the oc-48 transponder can be grouped into transmit (tx) and receive (rx) functions. the tx signals are: txdatap/n[0..3]: 4 differential lvds inputs for tx data. txclkp/n: a differential lvds input for tx clock. refclkp/n: a differential lvpecl input for tx reference clock. phase_initp/n: a differential lvds input for phase initializa- tion of the tx mux. phase_errp/n: a differential lvds output for phase error of the tx mux. the rx signals are: rxdatap/n[0..3]: 4 differential lvds outputs for rx data. rxclkp/n: a differential lvds output for rx clock. interfacing interfacing diagram tx signals the customer oc-48 framer drives the txdata and txclk inputs. in order to use dc coupling, the framer should be a +3.3 v lvds device. each of the inputs is terminated with 100 ? differential between lines in the transponder. the phase_err output is not true lvds, but is lvds level compatible, which uses a 330 ? to ground termination in the transponder. the phase_init input is lvds. in normal opera- tion, phase_initp is directly connected to phase_errp , and phase_initn is directly connected to phase_errn. these connections must be made on the customer board. wavelength 1310 nm total output power (as defined by iec: 50 mm aperture at 10 cm distance) 2 mw total output power (as defined by fda: 7 mm aperture at 20 cm distance) 180 w beam divergence 5 class 1 laser product iec complies with 21 cfr 1040.10 and 1040.11 fda top view pigtail sc or lc indication of laser aperture and beam
fiber optics v23816-n1018-c/l312, 3.3v, 4-line lvds parallel 2.5gbd transp.oc-48 sonet/sdh sr, 2km 11 the refclk input is a lvpecl input, which is driven by the customer clock source, which should be an lvpecl device. dc coupling is acceptable if the clock source is a +3.3 v lvpecl. the refclk input is terminated with 100 ? differential between lines in the transponder. it is necessary for the cus- tomer to provide the external 330 ? resistors to ground for the source termination. rx signals the customer framer accepts as input the rxdata and rxclk outputs of the transponder. in order to use dc coupling, the framer should be a +3.3 v lvds device. the rxdata and rxclk outputs of the transponder are not true lvds, but are lvds level compatible, which use a 330 ? to ground termina- tion in the transponder. if the framer does not have a 100 ? dif- ferential termination between lines, then the customer will have to supply the terminations on their board. line impedance for proper impedance matching, all lvds traces should be con- structed as a differential trace pair, with 100 ? characteristic impedance between the lines of each pair, and 50 ? character- istic impedance per line. the lvpecl traces should be con- structed as 50 ? per line. conversion of rx_mon output to a voltage with respect to ground mechanical size the outline size for the transponder housing is 2.3 in x 1.6 in x 0.54 inches. please refer to the outline drawing. fiber & connectors the transponder has fiber pigtails for both tx and rx. the tx pigtail is single mode fiber, 9 m/125 m. the rx pigtail is multi mode fiber, 50 m/125 m. each pigtail is terminated with a lc/pc or sc/pc optical connector with 0 o polish. the minimum bend radius of the fiber pigtails is 30 mm (1.18 inches), typical. the fiber length see ordering information on page 1, as measured from the transponder housing to the tip of the connector. interface connector the transponder interface connector is a 60 pin smt, dual row, header, 0.5 mm pitch, with ground blade, samtec part number qth-030-01-l-d-a. the appropriate mating connector for the customer pcb is a 60 pin smt, dual row, socket, 0.5 mm pitch, with mating alignment pins, samtec part number qsh-030-01-l- d-a. the internal blade of the connector should be connected to signal ground on the user ? s pcb. contact samtec for recom- mended pcb layout pattern for qsh connector. hostboard contact area following is the recommended board layout and hostboard con- tact area. board layout for detailed connector layout information, check http://www.samtec.com, and go to ? qsh ? connector. layout with reference to the spec of samtec connector qsh-030-01-*-d-a placement of all holes 1) outline shadow with maximal dimensions included are the tolerances of the transponder and the samtec connector 1) 1) detail x, 2:1 dimensions in mm [inches]
published by infineon technologies ag ? infineon technologies ag 2000 all rights reserved attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact the infineon technologies offices or our infineon technologies representatives worldwide - see our webpage at www.infineon.com/fiberoptics warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your infineon technologies offices. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. infineon technologies ag fiber optics wernerwerkdamm 16 berlin d-13623, germany infineon technologies, inc. fiber optics 1730 north first street san jose, ca 95112, usa infineon technologies k.k. fiber optics takanawa park tower 20-14, higashi-gotanda, 3-chome, shinagawa-ku to ky o 14 1, j a p a n hostboard contact area for the guaranteed emi-performance an optimal electrical con- tact between the transponder housing and the user's pcb sig- nal ground is necessary. for the user's pcb (hostboard) we recommend a full signal ground plane underneath the entire transponder housing (including the standoff area, the emi gas- ket area and the optional heatsink area). the transponder is equipped with an attached emi gasket. according to the drawing ? hostboard contact area ? the con- tact surface of the entire emi gasket should be connected to signal ground on the user's pcb. the area under the emi gas- kets (emi gasket area) should be gold flash or tin plated copper with no solder mask or other nonconductive coatings. the four mounting screws of the housing also must be con- nected to signal ground on the user's pcb. therefore the mounting screw areas should have square pads of gold flash or tin plated copper, that are connected to signal ground. these pads are located on the pcb opposite side to the transponder. use a torque wrench to tighten the mounting screws. the rec- ommended torque value is 10 2 ncm = 0.1 0.02 nm = 14.16 2.83 oz-in. with a higher or lower value, the emi-perfor- mance will deteriorate. the heatsink area under the center of the transponder is optional and could be used for critical ambient temperature or critical airflow. currently it is not a complete replacement for the regular heatsink. the contact area should be connected to signal ground. gold (au), tin or other metal platings are recom- mended for good heat transfer. any polymer coating will decrease the heatsinking performance. special heat transfer pads are in progress. for reliable heatsinking to the hostboard, the max. hostboard temperature must be lower or equal to the specified ambient air temperature. dimensions in mm [inches]

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